The nonvolatile semiconductor memory has an overall configuration, for example, as that shown in FIG. 1. In FIG. 1, N cell blocks 11.sub.1 to 11.sub.N (for example, eight blocks) each having multiple transistor cells are arranged in a row. The cell blocks 11.sub.1 to 11.sub.N are provided with bit line select circuits 12.sub.1 to 12.sub.N and sense amplifiers/sense buffers 13.sub.1 to 13.sub.N respectively.
A row address signal is supplied from a row address buffer 14 to each of the cell blocks 11.sub.1 to 11.sub.N via a row decoder 15. A column address signal is supplied from a column address buffer 16 to each of the bit line select circuits 12.sub.1 to 12.sub.N via a column address decoder 17. A voltage V.sub.S sent from a source power supply circuit 18 is applied to each of source electrodes of the transistor cells of the cell blocks 11.sub.1 to 11.sub.N.
FIG. 2 shows the cell block 11, one of the cells blocks in the aforesaid nonvolatile semiconductor memory, and its peripheral circuitry. In FIG. 2, components identical to those in FIG. 1 bear the same reference numerals, of which a description will be omitted. In FIG. 2, the bit line select circuit 12 comprises n-channel MOS field-effect transistors Q1 to Qn. Column address signals Y1 to Yn are fed from the column decoder 17 to the gates of the transistors Q1 to Qn.
The cell block 11 comprises a total of n by n field-effect transistors Q11 to Qnn having floating gates and control gates. The gates of n transistors Qi1 to Qin (where, i=1, 2, etc., and n) arranged in tandem are provided with row address signals Xi sent from the row decoder 15 via word lines.
The drains of the n transistors Q1i to Qni arranged in tandem are connected to the drains of the transistors Qi in the bit line select circuit 12 via bit lines. Voltage from the source power circuit 18 is applied to each of the sources of the transistors Q11 to Qnn. A cell amplifier 13a and a write buffer 13b are connected to each of the sources of the transistors Q1 to Qn.
In the foregoing semiconductor memory, when row addresses Xi and column addresses Yi are selected for writing, data read from the write buffer 13 are written in the transistors Qij of the cell blocks 11.sub.1 to 11.sub.N. Writing is performed simultaneously on one bit per each of the cell blocks 11.sub.1 to 11.sub.N or a total of N bits designated with the row addresses and column addresses. Data erasing is performed concurrently on all transistors in the cell blocks 11.sub.1 to 11.sub.N.
In a flash memory, information is retained depending on the presence or absence of a charge in a memory cell. FIG. 3 shows an example of a structure of a memory cell. As shown in FIG. 3, a gate has a two-layered structure consisting of a control gate (CG) 25 and a floating gate (FG) 24. The control gate 25 is connected to a word line WLi and a drain (D) 23 is connected to a bit line BLi. Reference numeral 26 denotes a tunneling oxide film.
The flash memory is broadly divided into two types of what are referred to as NOR and NAND. These types differ from each other in a method of writing, reading, or erasing information into or from a memory cell. Taking the NOR type flash memory as an example, writing, reading, or erasing information into or from a memory cell will be described below.
When information is to be written in a memory cell having the aforesaid structure, as shown in FIG. 4, the word line WLi is set to Vpp (approx. 12 V), the bit line BLi is set to approx. 6 V, and the source S is set to 0 V. High voltage is then applied to the control gate CG and drain D. Current then flows into the memory cell. Part of the electrons flowing through the memory cell are accelerated due to the high electric field in the vicinity of the drain D, gain energy, and then goes beyond the energy barrier of an insulating film of the floating gate. The electrons are finally injected into the floating gate FG. The floating gate FG is not electrically coupled with other circuits, so it therefore can retain charges on a semi-permanent basis.
When information is to be read from a memory cell, as shown in FIG. 5, the word line WLi is set to Vcc (about 5 V), the bit line BLi is set to about 1 V, and the source S is set to 0 V. The memory cell is then selected by specifying the word line WLi and bit line BLi. The threshold value of the cell transistor varies depending on the charges retained in the floating gate FG. Current flowing through the selected memory cell varies depending on the information stored therein. The information therefore can be read out by detecting and amplifying the current.
The voltage levels of the control gate CG, drain D, source S, and substrate PS in the aforesaid operative states are set to the values listed in Table 1.
TABLE 1 ______________________________________ Voltages in modes in a prior art CG D S PS ______________________________________ Reading Vcc to 1 V 0 V 0 V Writing Vpp to 6 V 0 V 0 V Erasing 0 V Float Vpp 0 V ______________________________________
When information is to be erased from a memory cell, as shown in FIG. 6, the word line WLi is set to about 0 V and the bit line BLi is opened. In this state, the drain D is opened, about 0 volt is applied to the control gate CG, and a high voltage of about 12 volts is applied to the source S.
Since a high voltage is applied to the source S, deep diffusion is required in order to increase the resistivity of the diffused layer in the source. This hinders reduction in cell area.
For divided erasing, it is required that the Vss line in the source must partly have a different voltage. This leads to disconnection or an increased number of drive circuits. Eventually, chip size increases.
A solution to the above problem is to apply a negative voltage to the word line WLi. To be more specific, as shown in FIG. 7, a negative voltage (about -10 V) is applied to the control gate CG and Vcc (about 5 V) is applied to the source S. The drain D is opened. Erasing is then executed.
In this case, since a low voltage is applied to the source S, the resistivity of the source need not be intensified. This contributes to reduction in cell size. Partial erasing is enabled by selectively applying negative voltage to the control gates CG.
The aforesaid erasing method is a source erasing method in which charges in the floating gate FG are routed to the source. A channel erasing method is also available, wherein charges in the floating gate are routed to a channel; that is, a substrate. Even in this method, negative voltage is applied to the control gate. The channel erasing method is sometimes employed for the aforesaid NAND-type flash memory.
FIGS. 8 to 11 show the states of a memory cell with voltage applied according to various erasing methods. In FIGS. 8 to 11, the memory cell is an n-channel transistor.
FIG. 8 shows a state in which positive voltage is applied according to a channel erasing method. The drain D and source S are opened, and the control gate CG is set to 0 V. The high voltage Vpp is applied to the P well equivalent to a channel. In channel erasing, a triple-well structure shown in FIG. 8 is adopted because positive bias is applied to the channel.
FIG. 9 shows a state in which a positive voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to 0 V. The high voltage Vpp is applied to the source S. The substrate is opened or set to 0 V.
FIG. 10 shows a state in which a negative voltage is applied according to the channel erasing method. The drain D and source S are opened, and the control gate CG is set to a negative voltage V.sub.BB. A positive voltage Vcc is applied to the p well equivalent to a channel. V.sub.BB -Vcc is applied between the control gate CG and channel.
FIG. 11 shows a state in which negative voltage is applied according to the source erasing method. The drain D is opened, and then the control gate CG is set to the negative voltage V.sub.BB. The source S is set to the positive voltage Vcc.
The resistivity of a junction in a source region can be improved by applying negative voltage to a control gate during erasing. This has the advantage of enabling reduction of a cell area. It is, however, a big problem how to realize application of negative voltage to the control gate.
It is, for example, conceivable to apply negative voltage from a row decoder to word lines. The voltage to be applied to a word line is changed depending on whether the word line is selected or not. In a flash memory, the voltage to be applied to a word line must be varied depending on whether the read mode or write mode is selected. When the row decoder is used to apply a negative voltage, the voltage to be applied to a word line must be changed to a negative voltage. A word line selected in the read or write mode has a higher voltage than other unselected word lines. For erasing, however, the selected word line must have a lower voltage than the unselected word lines. The level of applied voltage must therefore be reversed depending on the logic of selected or unselected word lines. This results in complex circuitry, making downsizing in possible.
A flash memory includes an internal power switching circuit for switching supply voltages depending on a mode. A conventional internal power switching circuit has a simple circuitry but is likely to cause a latch-up phenomenon. The switching speed is decreased in order to avoid the latch-up phenomenon. This contradicts efforts to speeding up processing.
Furthermore, for negative voltage erasing, bias voltage must be applied to a substrate or part of a well. A conventional substrate bias circuit is realized with a p-channel depletion-type transistor. The manufacturing process is complex and downsizing is hard to do.